Michigan faculty and students will present seven papers at the 2014 Symposium on VLSI Circuits, a number that exceeds any other academic institution or company. The seven papers range from a millimeter-scale wireless imaging system, to a chip that can decipher an image in a manner similar to the human brain, to continued optimization of the circuits we use every day, as well as circuits that will fuel the future Internet of Things. One of the papers, Low Power Battery Supervisory Circuit with Adaptive Battery Health Monitor, has been selected as a Symposium Technical Highlight.
All of the research being presented (described below) focuses on the challenge of getting the absolute best performance from the tiniest circuits, sensors, and electronic devices being made today. Michigan researchers were early leaders in the area of energy-efficient circuits, as well as complete miniature low-power systems. They have continued this legacy, while breaking new ground with systems such as the millimeter-scale wireless imaging system by Kim, et al.
Most of the students and faculty representing Michigan are members of the Michigan Integrated Circuits Laboratory (MICL), including Prof. David Blaauw, Prof. Michael Flynn, Dr. Yoonmyung Lee, Prof. Dennis Sylvester (Director of MICL and a member of the Technical Program Committee for the Symposium), and Prof. Zhengya Zhang. Prof. Prabal Dutta is a member of the Advanced Computer Architecture Laboratory.
The strong presence of Michigan at the VLSI Symposium this year is not a fluke. Michigan researchers regularly present among the most papers at the top conferences in circuits. Just last year, Prof. Blaauw and Prof. Sylvester were recognized by ISSCC as being top contributors to that conference [read more]. When asked what accounts for their high productivity, Prof. Sylvester mentioned the strong team environment of the MICL faculty, who work extremely well with each other while also forming strong research partnerships with other talented researchers.
At the conference, held June 9-13, Prof. Blaauw will present the talk, “Overview and Advances in Energy Efficient Digital Design” as part of a Short Course on Advanced Energy Efficient Digital Design, and Prof. Sylvester will co-chair a session on Medical Imaging..
Following is a summary of the Michigan research being presented:
Low Power Battery Supervisory Circuit with Adaptive Battery Health Monitor (Selected as a Symposium Technical Highlight)
Inhee Lee, Dr. Yoonmyung Lee, Prof. Dennis Sylvester, Prof. David Blaauw
|Michigan faculty are leading the Internet of Things revolution (ie, an interconnected world through the use of wireless sensor nodes) with their breakthroughs in low power and miniature circuits and systems. However, managing when to use precious battery resources remains a key challenge.
This paper describes a battery supervisory circuit (BSC) for wireless sensor nodes that determines how much energy has been harvested and transferred to the sensor’s battery, and allows the system to work only when sufficient threshold voltage has been reached to ensure reliable operation. When tested with a 2μAh battery and 11μA sensor system, their BSC increased the usable battery voltage range by 2.7×.
A Millimeter-Scale Wireless Imaging System with Continuous Motion Detection and Energy Harvesting
Gyouho Kim, Dr. Yoonmyung Lee, Zhi Yoong Foo, Patrick Pannuto, Y.-S. Kuo, Ben Kempke, Mohammed Ghaed, Suyoung Bang, Inhee Lee, Yejoong Kim, Seok-Hyeon Jeong, Prof. Prabal Dutta, Prof. Dennis Sylvester, Prof. David Blaauw
Visual imaging is a highly desired feature for wireless sensing applications such as biological monitoring and surveillance. Recent advances in low power circuit techniques and integration have resulted in self-sustaining wireless sensor nodes as small as 1mm3. However, achieving a complete visual sensing system in a similar volume is challenging due to physical difficulties in integrating optics and the high power consumption of key components such as the image sensor and RF transmitter.
This work introduces a 2×4×4mm3 imaging system complete with visual imaging and ultra-low power motion detection, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. The overall system sleep power is 304nW with motion detection enabled, allowing energy-autonomous operation with 10klux of background lighting, which is a typical daytime condition on a window or light source surface.
A 6.67mW Sparse Coding ASIC Enabling On-Chip Learning and Inference
Jung Kuk Kim, Phil Knag, Thomas Chen, Prof. Zhengya Zhang
Application-specific integrated circuits (ASIC) are integrated circuits that have been adapted to specific applications – such as auto emission control, sensors for environmental monitoring, motion detectors, and mobile phone control circuits – as opposed to a general purpose computer chip that must perform many applications.
This paper describes an ASIC that enables on-chip learning and inference through a machine learning technique known as sparse coding. It mimics the human brain’s ability to make sense of objects and complete scenes, and is the first fully integrated sparse coding ASIC that consists of 256 digital neurons, 64K feed-forward synapses, and 64K feedback synapses. The chip is capable of both unsupervised learning and inference on-chip, and demonstrates its potential for embedded vision processing tasks.
A 266nW Multi-Chopper Amplifier with 1.38 Noise Efficiency Factor for Neural Signal Recording
Yen-Po Chen, Prof. David Blaauw, Prof. Dennis Sylvester
Spectacular advances have been made in brain machine interfaces. ECE researchers were pioneers in neural interface technology, which is used to treat disorders such as deafness, paralysis, epilepsy, and Parkinson’s Disease; and they have continued to advance the field. Recently, the recording of human body electrical signals for use in rehabilitation, human movement sciences, and other applications has attracted growing attention.
This paper describes a low power high efficiency neural signal recording amplifier with a novel multi-chopper technique implemented in 180nm CMOS. The device’s 1.38 noise efficiency factor is the best reported among current state-of-the-art amplifiers used in neural signal recording.
15.4b Incremental Sigma-Delta Capacitance-to-Digital Converter with Zoom-in 9b Asynchronous SAR
Sechang Oh, Wanyeong Jung, Kaiyuan Yang, Prof. David Blaauw, Prof. Dennis Sylvester
Capacitance-to-digital converters (CDC) are used in a variety of industrial, automotive, and consumer applications. They enable touch pads for computers and touchscreens on mobile and other electronic devices, and are used in wireless microsystems to measure pressure, proximity and movement of objects, and humidity. When used in wireless microsystems where battery life is very limited, it is important that the CDC require low conversion energy yet attain high resolution.
The authors designed a zoom-in CDC that achieves 94.7dB SNR and 33.7μW power consumption with 175fJ/conv-step at 1.4V supply. Compared to other CDCs in the literature, this work achieves a favorable balance of low power consumption and quality resolution.
An N-path Filter Enhanced Low Phase Noise Ring VCO
Chunyang Zhai, Jeffrey Fredenburg, John Bell, Prof. Michael Flynn
Voltage-controlled oscillators (VCO) are used in several key functions in circuits. For example, they can help maintain a stable frequency in a circuit (important for communication devices); they are used in phase-locked loops for radio receivers; and they are used in function generators for electronic test equipment.
In this work, the researchers fabricated a prototype N-path filter enhanced voltage-controlled ring oscillator (NPFRVCO) that performs significantly better than a comparable coupled ring VCO without N-path filtering. The overall performance of this NPFRVCO approaches state-of-the-art LC oscillators, while also taking advantage of the smaller area and wider frequency tuning range that it inherits from the CMOS ring oscillator structure.
A 4.68Gb/s Belief Propagation Polar Decoder with Bit-Splitting Register File
Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Prof. Zhengya Zhang
Polar decoding is a relatively new technique that can theoretically be used to achieve capacity-achieving, or perfectly efficient, code sequences. This capacity-achieving capability was first suggested by Claude Shannon (the “Father of Information Theory”) back in 1948, though not explicitly proven until 2009.
This paper describes the first belief propagation (BP) polar decoder fabricated in silicon. The chip achieves a 34×, 2.8×, and 5.2× improvement in throughput, energy efficiency, and area efficiency, respectively, over the latest successive cancellation (SC) polar decoder ASIC, when normalized to 65nm and 1.0V. The results prove the potential of polar codes for future communication and storage systems.
About the Symposium
Since its first meeting in 1987, the VLSI Circuits Symposium has become one of the premier conferences in circuit design and VLSI. It is held in conjunction with the Symposium on VLSI Technology to provide opportunities for technology people and circuit and system designers to interact with each other.
In addition to the papers already mentioned, Michigan researchers will present the invited paper, “IoT Design Space Challenges: Circuits and Systems,” by D. Blaauw, D. Sylvester, P. Dutta, Y. Lee, I. Lee, S. Bang, Y. Kim, G. Kim, P. Pannuto, Y.-S. Kuo, D. Yoon, W. Jung, Z. Foo, Y.-P. Chen, S. Oh, S. Jeong, and M. Choi, as part of the Technology/Circuits Joint Focus Session.